1. Field of the Invention
The present invention relates to a manufacturing method of a solid-state imaging device. In particular, the invention relates to a manufacturing method of a solid-state imaging device having a vertical overflow drain structure.
2. Description of the Related Art
CCD solid-state imaging devices and MOS solid-state imaging devices are popular solid-state imaging devices for digital cameras, and solid-state imaging devices of either type employ photodiodes as photodetectors. The photodiodes generate charges in accordance with the quantities of incident light, and carriers of one type (usually electrons) produced by the photoelectric conversion are read out via vertical transfer passages which are CCDs or MOS circuits.
It is desirable to fully remove the storage charges of the photodiodes before a start of shooting. The vertical overflow drain structure capable of fully removing the storage charges of all pixels at the same time is known as a structure of a solid-state imaging device.
In the vertical overflow drain structure, an npn structure is formed in a semiconductor substrate in its depth direction and the storage charges of all pixels can be cleared at the same time by eliminating a potential barrier formed by the middle p-type layer by applying a substrate bias (charge-removal-into-substrate shuttering function).
Furthermore, the potential barrier height can be changed by changing the bias voltage applied to the substrate. And the saturation charge amount of the photodiodes can be changed by changing the potential barrier height.
When receiving strong light, photodiodes generate excess charges above the saturation charge amount. If the excess charges leak into adjacent photodiodes, vertical transfer passages, etc., the image quality of an image taken is deteriorated. An overflow drain that enables removal of only excess charges into the substrate is realized by employing the charge-removal-into-substrate shutter structure and applying a substrate bias so as to leave a potential barrier. The inter-pixel blooming (a phenomenon that excess charges of part of the pixels flow into other pixels, whereby the latter pixels are saturated electrically and the screen looks whitish) can be prevented by sweeping away excess charges above the saturation charge amount into the substrate.
A solid-state imaging device having a vertical overflow drain structure in which an overflow barrier is formed by two p-type layers having different concentrations is proposed to reduce a variation of the saturation charge amounts of the photodiodes (JP-A-2004-228140).
On the other hand, in recent years, a manufacturing method of a solid-state imaging device has come to be employed in which oblique ion implantation is performed to form, with high controllability, an impurity layer at a shallow position in a semiconductor substrate (e.g., JP-A-11-40794).
In recent years, the level of miniaturization of solid-state imaging devices has been increased further, which has produced a tendency that the size of the photodetecting portions (photodiodes) is decreasing (i.e., the area ratio of the photodetecting portions to the vertical transfer regions is decreasing). As a result, each pixel is saturated more easily when receiving strong light. The inter-pixel blooming is thus more prone to occur than before.
To prevent the inter-pixel blooming using the overflow drain, it is necessary to increase the ability to remove excess charges by increasing the sweep-into-substrate voltage. However, if the sweep-into-substrate voltage is increased in a situation that the amount of charge that can be stored in each pixel is decreased by pixel size reduction, it becomes more difficult to secure a necessary amount of charge each pixel can handle (i.e., a necessary saturation charge amount), which is contrary to the intention. 
To prevent the inter-pixel blooming without increasing the sweep-into-substrate voltage, it is necessary to increase the impurity concentration of inter-pixel isolation regions (also function as channel stoppers for preventing channel leakage between pixels and vertical transfer gates) provided between pixels and to thereby increase the charge storage amount by indirectly making the potential of the photodetecting portions deeper and enhance the function of preventing formation of charge leakage paths. However, where the impurity concentration of the inter-pixel isolation regions is increased, if high-temperature treatment (for gate oxidation, for example) is performed in a later manufacturing step, the inter-pixel isolation regions spread horizontally, leading to a problem that the area of the photodetecting portions is decreased. Decrease in the area of the photodetecting portions reduces the saturation charge amount of each pixel and makes it difficult to secure a necessary dynamic range.
In the case of solid-state imaging devices for receiving long-wavelength light such as infrared light, carriers are generated in a deep place in the substrate. It is therefore necessary to form plural inter-pixel isolation regions in multiple layers at different positions in the substrate depth direction and to thereby allow the photodetecting portions to effectively take carriers generated in a deep place in the substrate and prevent charge leakage between pixels in the deep place in the substrate. Where plural inter-pixel isolation regions are thus formed in multiple layers at different positions in the substrate, each of the inter-pixel isolation regions spreads horizontally as a result of later heat treatment, leading to decrease in the area of the photodetecting portions as in the above-described case.